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UDC 621.396(024)

© Berezin V. V., Zinkevich A. V. , 2010

Examination of Response Time to Interruptions for the System on Chip with the Soft-Processor NiosII

One of the key problems concerning design at a system level consists in an in-crease of the system complexity which calls for operation with abstractions and specifications of a higher level. In developing devices operating in a real time mode the important factor is speed of response. The purpose of the paper is to define the potential of the soft-processor NIOS II in the course of processing of interruptions depending on its configuration and also to estimate occupied re-sources of CPLD.

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